Field of the Invention
The present invention relates to terminations for multilayer electronic support structures such as interposers, and to methods of manufacturing of same.
Description of the Related Art
Driven by an ever greater demand for miniaturization of ever more complex electronic components, consumer electronics such as computing and telecommunication devices are becoming more integrated. This has created a need for support structures such as IC substrates and IC interposers that have a high density of multiple conductive layers and vias that are electrically insulated from each other by a dielectric material.
The general requirement for such support structures is reliability and appropriate electrical performance, thinness, stiffness, planarity, good heat dissipation and a competitive unit price.
Among the high density leading technologies used to interconnect the Substrate to Chips is the well-established “Flip Chip” technology, in which solder bumps, lead-free solder bumps, or copper bumps having solder or lead-free solder on their tips, are grown on the chip terminating pads and the chip is then flipped over to interconnect its bumps with the pads on the top surface of the substrate. As chip bumps and pitches become denser, advanced substrates are sometimes equipped with bumps of their own to assist with the interconnection to the chip bumps. Such bumps on the substrate pads are also known as “SoP” (Solder on Pad”) bumps—and usually consist of solder or lead-free solder. The SoP bumps are generally applied to the substrate terminating pads by stencil printing followed by reflow, or by electroplating processes followed by reflow or by solder balls dropped onto substrate fluxed pads. Such bumps are usually “coined” by applying heat and pressure to generate a top flat surface on the bumps, which can assist with the placement of the bumps from the die side.
A minimum bump array pitch on the substrate of 140 μm to 150 μm is currently used for solder bumps in many applications, and 50 μm to 60 μm pitch that correspond with the introduction of 14 nm node silicon are anticipated to be needed.
Generating solder bumps on the substrate in ever tighter pitches is tricky in that the current methods of stencil printing, solder ball drops or solder bump electro plating are required to be more and more accurate and more expensive in order to overcome the risk of shorting between nearby connections at the finer pitches.
U.S. Pat. No. 9,049,791 to Hurwitz and Huang titled “Novel Terminations and Couplings Between Chips and Substrates” and filed on 7 Jun. 2013 discloses a multilayer composite electronic structure comprising at least one pair of feature layers extending in an X-Y plane, each adjacent pair of feature layer being separated by an inner via layer, the via layer comprising via posts that couple adjacent feature layers in a Z direction perpendicular to the X-Y plane, the via posts being embedded in an inner layer dielectric, the multilayer composite structure further comprising terminations consisting of an outer layer of via pillars embedded in an outer dielectric material, thinned to expose the ends of the outer layer of via pillars.
U.S. Ser. No. 13/912,652 to Hurwitz teaches copper via posts that are embedded in dielectric and then thinned so that the ends of the copper via posts are flush with the surface of the dielectric. Typically, the thinned outer layer of via pillars with exposed ends embedded in an outer dielectric material that is substantially planar with a roughness of less than 3 microns and the exposed outer layer of via pillars is interconnectable with flip chip bumps. The ends of the via pillars which are flush with the dielectric in which they are embedded, may be connected to the flip chip bumps by a solderable metal through reflow or by a Z-conductive anisotropic adhesive material.
It will be appreciated that the contact area between the solder bumps and the copper via posts is limited to the cross-sectional area of the copper via posts. All the contacts are in a single plane. This leads to a certain susceptibility of disconnected contacts and electrical open failures.
U.S. Ser. No. 14/150,683 to Hurwitz and Huang titled “Substrates with Ultra Fine Pitch Flip Chip Bumps” filed on 8 Jan. 2014 describes a different approach. Here a multilayer composite electronic structure comprising feature layers extending in an X-Y plane is again described, wherein each adjacent pair of feature layers is separated by an inner via layer that comprises via posts that couple adjacent feature layers in a Z direction perpendicular to the X-Y plane, the via posts being embedded in an inner layer dielectric. In the structures disclosed, the multilayer composite structure further comprises at least one outer layer of terminations comprising at least one micro bump wherein the at least one micro bump comprises a via pillar capped with a solderable material. The solderable material on the micro bump fuses with the solder bumps of the flip chip package to be attached to the chip. This provides additional solderable material and aids adhesion. This solution is somewhat more expensive than other termination technologies because of the additional processing and the different compositions of solderable materials that are required.
U.S. Ser. No. 14/163,084 to Hurwitz and Huang titled “Substrates with Protruding Copper Termination Posts” was filed on 24 Jan. 2014. It teaches a multilayer composite electronic structure comprising feature layers extending in an X-Y plane, each adjacent pair of feature layers being separated by an inner via layer, the via layer comprising via posts that couple adjacent feature layers in a Z direction perpendicular to the X-Y plane, the via posts being embedded in an inner layer dielectric, the multilayer composite structure further comprising at least one outer layer of terminations comprising a two dimensional array of copper posts that is only partially embedded in an outer layer of dielectric such that part of each copper post protrudes beyond surface of the outer layer of dielectric.
This approach enables enhanced bonding, in that solder bumps of a chip may coat and bond with not just the top surface of the protruding ends but also the protruding side walls thereof. This provides a larger surface area for bonding and also since the solder—post interface is not linear, it is less likely to simply shear and fail. This approach also supports the copper pillar adhesion level to the substrate since it is anchored to the substrate at its base as well as by the non-protruding side walls. Nevertheless, due to the relatively large thickness of copper pillars as compared to the conductor layer and since each of the copper pillars must be accurately aligned on an underlying conductor layer, such pillars are subject to separation spacing limitations that can adversely affect their application in tight pitch flip chip devices. Furthermore, it will be appreciated that an additional copper pillar layer increases the number of process steps required for manufacturing such substrates thereby increasing fabrication costs and lowering yields.
Despite the various developments with interposer terminations, there is a constant drive towards tighter pitch conductors with terminations to which flip chip devices can be attached by solder bumps avoiding additional structures such as copper pillars which would require additional processing and alignment steps and add undesirable thickness.